Xref: utzoo comp.arch:6881 comp.sys.next:342 Path: utzoo!utgpu!water!watmath!clyde!att!osu-cis!tut.cis.ohio-state.edu!mailrus!ames!oliveb!amdahl!mat From: mat@amdahl.uts.amdahl.com (Mike Taylor) Newsgroups: comp.arch,comp.sys.next Subject: Re: RISC v. CISC (really comments on many postings: LONG) Message-ID: Date: 28 Oct 88 01:04:52 GMT References: <156@gloom.UUCP> <6865@winchester.mips.COM> <468@oracle.UUCP> <7038@winchester.mips.COM> Organization: Amdahl Corporation, Sunnyvale CA Lines: 25 In article <7038@winchester.mips.COM>, mash@mips.COM (John Mashey) writes: > In fact, it might be instructive for the newsgroup for somebody > to post a description of what a 5990 memory hierarchy looks like in > more detail. Your wish is my command. Each processor has a 64K byte instruction cache and a 64K byte operand cache, equipped with their own TLBs. Implemented in 16K chips, 2.8 ns. access (chips also have 1200 logic gates). From memory, I think it is organized as 128-byte lines, 4-way set associative, with about 15 cycles miss penalty. Main storage is up to 512 megabytes of 55ns. 256K SRAM, accessed as cache lines and interleaved. Below main storage, there is expanded storage and I/O. Expanded storage is up to 2GB of 1M DRAM, accessed as pages. I/O consists of up to 128 channels. 2 are byte-multiplexor channels, another 30 are either, and the remainder are only block-multiplexor channels. Block mux channels go up to 4.5 mB/sec. A typical configuration has about 5 GB/MIPS of DASD installed. So an average 5990-1400 at (say) 105 370 MVS MIPS would have about 500GB of DASD. Many of our customers have DASD farms in the terabyte league, however, plus tape, non-volatile electronic storage ("EDAS"), etc. -- Mike Taylor ...!{hplabs,amdcad,sun}!amdahl!mat [ This may not reflect my opinion, let alone anyone else's. ]