Path: utzoo!attcan!uunet!lll-winken!lll-tis!ames!ll-xn!husc6!cmcl2!adm!smoke!gwyn
From: gwyn@smoke.BRL.MIL (Doug Gwyn )
Newsgroups: comp.unix.questions
Subject: Re: *nix performance
Message-ID: <8734@smoke.BRL.MIL>
Date: 22 Oct 88 20:44:24 GMT
References: <9902@ico.ISC.COM> <736@starfish.Convergent.COM> <1901@van-bc.UUCP> <1488@ssc.UUCP> <168@ernie.NECAM.COM> <1279@umbc3.UMD.EDU>
Reply-To: gwyn@brl.arpa (Doug Gwyn (VLD/VMB) <gwyn>)
Distribution: na
Organization: Ballistic Research Lab (BRL), APG, MD.
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In article <1279@umbc3.UMD.EDU> brian@umbc3.UMD.EDU (Brian Cuthie) writes:
>DMA places the processor in a HOLD state while the transfer takes place.

This is true for a "cycle stealing" implementation of DMA, but other
implementations are possible (for example, using dual-ported memory).