Xref: utzoo comp.unix.microport:1855 comp.unix.xenix:3736 Path: utzoo!utgpu!water!watmath!clyde!att!osu-cis!tut.cis.ohio-state.edu!cs.utexas.edu!wasatch!utah-gr!uplherc!sp7040!obie!wes From: wes@obie.UUCP (Barnacle Wes) Newsgroups: comp.unix.microport,comp.unix.xenix Subject: Re: *nix performance Summary: Boy, has this fellow been mislead! Message-ID: <233@obie.UUCP> Date: 24 Oct 88 05:35:34 GMT References: <9902@ico.ISC.COM> <736@starfish.Convergent.COM> <1901@van-bc.UUCP> <1279@umbc3.UMD.EDU> Distribution: na Organization: the Well of Souls Lines: 88 In article <1279@umbc3.UMD.EDU>, brian@umbc3.UMD.EDU (Brian Cuthie) writes: > .... Besides, I know what re-entrant instructions are (and > besides, they're "restartable instructions", but that's a different point), OK, what are re-entrant instructions? I know what re-startable instructions are, and they have NOTHING to do with re-entrant CODE! > but what the !%^%@ is a re-entrant operating system. A re-entrant operating system would be one that is implemented with all of the system calls being re-entrant. This means, for instance, that while one task has blocked on a write() call that must wait for the i/o operation to complete, another task may call write() without crashing the system. MS-DOS is not re-entrant; if you have two calls to a DOS system call active at once, the system will not be able to return to the first program that made the call. This is why networks for the IBM PC have to replace most of the operating system (on the server, at least) - the server must be able to open files, etc., for more than one program at a time. > Can you name one?? I bet not. Sure: Unix. You loose. Should I name more? Minix. VAX/VMS. RT-11, RSTS/E, RSX-11 for the PDP-11. Turbodos and MP/M, to go back a ways in the micro world. OS-9. OS/2, for that matter. Had enough? > The problem with DMA on the PC is simple. DMA channel 0 is programmed to > periodically paw through RAM to effect a refresh. This, of course, is not true on the PC/AT, which has dedicated memory refresh hardware. > Keep in mind that DMA is significantly faster than CPU transfers, even with > caching, because the DMA chip places the memory address on the bus and then > asserts the READ or WRITE line while simultaniously asserting the DMA ACK > line. This also is not true on the PC/AT. Quoting from "The IBM PC From the Inside Out," Sargent & Shoemaker, p. 247: "The AT has dedicated DRAM refresh circuitry, which frees up DMA channel 0 for general use. In fact, you can use channels 0 and 1 to block move data within one 64-kilobyte RAM area while the 80286 does something else. However, since the 80286 moves blocks faster and can work with 16 bits at a time, this is not particularly useful. In fact, the 80286 has string I/O instructions (rep insw and rep outsw) that transfer data between RAM and I/O faster than the 8237A's can, and the AT uses this feature to transfer 512-bytes sectors to and from the hard disk controller." > Since the peripheral requesting DMA is well aware of who he/she is and knows > that if the memory WRITE line is asserted it must be a peripheral READ (and > vice versa) the transfer takes place in exactly ONE memory cycle. Wrong again. Again quoting from Sargent & Shoemaker, p. 244: "The initial byte transfer takes place in five clock periods, but subsequent transfers occur in three period (630 nanoseconds on the PC)." > Observe > that this would be twice as fast as the CPU since it requires, at best, one > cycle to read the byte from the peripheral and one cycle to write it > to memory. Of course the above argument holds for 16 or 32 bit words also, > so long as the memory, peripheral and DMA controller are all willing > to participate. This, of course, does not apply to the '286 and '386 INS and OUTS instructions. These instructions move {bytes,words} between memory and i/o ports in 5 cycles/{byte,word}. The big performance win with this is that the INS and OUTS instructions run at the processor speed, while the 8237 is restricted to a 5 Mhz clock speed. Mr. Cuthie, you do not seem to be very knowledgable about the PC architecture. Of course DMA sounds more "high performance" but the DMA controller on the 286 and 286-based AT clones on the market right now is pretty much useless, due to the incredibly slow speed it operates at. Perhaps you should study more before taking somebody to task in a public posting?!? Wes Peters -- Copyright 1988 Wesley R. Peters. Permission is granted to distribute this work in its entirety as long as it is not modified in any way, and this copyright remains intact. No rights other than those expressed here are granted. "How do you make the boat go when there's no wind?" -- Me