Path: utzoo!utgpu!water!watmath!clyde!att!osu-cis!tut.cis.ohio-state.edu!mailrus!ames!pasteur!ucbvax!hplabs!hp-sde!hpcuhb!hpihoah!fotland
From: fotland@hpihoah.HP.COM (Dave Fotland)
Newsgroups: comp.arch
Subject: Re: RISC v. CISC (was The NeXT problem)
Message-ID: <4420007@hpihoah.HP.COM>
Date: 25 Oct 88 22:44:27 GMT
References: <156@gloom.UUCP>
Organization: Hewlett Packard, Cupertino
Lines: 30


>Based on parameters of Berkelely RISC I or II, the register-saving
>might take on the order of 0.1 msec.  If the quantum size is set to
>be in the range claimed to be typical in the Peterson and Silberschatz
>OS book, i.e. 10 to 100 msec, then we see that the register-saving
>issue for a RISC with lots of regiters has probably been greatly
>overemphasized.

>Comments?

>   Norm Matloff
----------

This assumes all your processes are compute bound and run for the whole
time slice.  In commercaial applications there are very few instructions
between system calls and these frequently block, causing a contect switch.

If you only execute 10,000 instructions between context switches (about
1 msec) then a .1 msec overhead for saving and restoring the registers is
a big deal.

If you are only interested in workstations running mainly single 
compute bound jobs then register windows don't cost very much performance,
but if you want to build a general purpose architecture that can also be
used for large commercial systems then you probably want to leave them out.

Also, if you want to build a general purpose system that can be used for
real time applications, that .1msec in your interrupt latency could be
a problem.

-David Fotland