Path: utzoo!yunexus!geac!syntron!jtsv16!uunet!sco!seanf
From: seanf@sco.COM (Sean Fagan)
Newsgroups: comp.arch
Subject: Re: Mainframe channels  vs.  DMA  vs.  NeXT
Keywords: Another Cyber discussion!
Message-ID: <1594@scolex>
Date: 27 Oct 88 19:15:00 GMT
Article-I.D.: scolex.1594
References: <10778@reed.UUCP>
Reply-To: seanf@sco.COM (Sean Fagan)
Organization: The Santa Cruz Operation, Inc.
Lines: 45

In article <10778@reed.UUCP> mdr@reed.UUCP (Mike Rutenberg) writes:
$I equate channels with special IO coprocessors that can request things
$from memory without "main" processor interaction.  I believe the
$IBM 3033 uses 801s as channel processors.  How is this all set up?
$Does the system have multiported memory so that the 370 can get at
$it from one end while the channel controllers get at it from the
$other?  Since the 801 is a general purpose processor, that would
$suggest that the channel controller will have customized programs
$for the different peripherals that it feeds.

I don't know beans about IBM equipment, but CDC does (or did) this with the
Cyber series.  The 170-state machines can have one or two processors, up to
128K 60-bit words of memory, and 10 or 20 Peripheral Processors (PP's).  The
memory is, I believe, quad-ported (each group of 10 PP's share a single ALU,
and share it in rotation.  And, yes, each of the PP's is a (more or less)
general purpose processor (people have written PacMan-like games, baseball,
graphics drivers, etc., in PP-code, since the PP's control the console).
Generally, to do any sort of I/O on a Cyber, you write your request into
memory location 0 (what?! Dereference NULL?!), the PP's scan all jobs
location 0's, see the change, and do it.  You can optionally be suspended
from execution while the I/O is being done.

$Questions
$=========
$
$The NeXT box seems to have a big DMA controller and a 68030 competing
$for slow DRAM memory access - Does it seem reasonable to anyone that all
$10 (or 12?) DMA could be doing something useful without slowing the
$68030 to a crawl?  [pissing in the wind question -->] Other than that
$they might need custom hardware for special IO interfaces like the
$printer, might they have gotten away with 2 or 4 DMA channels?

Well, one thing which I *think* could be done on the NeXT machine is this:
put in a special I/O card, that talks to a disk or whatnot.  Give a a goodly
supply of private memory (for buffering), and, oh, maybe 4K or so of
dual-ported memory.  Have the card do caching all on its own, and, when the
CPU(s) want I/O done, request from the I/O card.  The data will be put into
the shared memory, and worked with.
(Yes, I realize that this has problems, but I think it's a good start.)

Anybody want to write the drivers for it? 8-)
-- 
Sean Eric Fagan  | "ld runs like a turtle out of antartica"
seanf@sco.UUCP   |     Steven Ryan (smryan@garth.UUCP)
(408) 458-1422   | Any opinions expressed are my own, not my employers'.