Path: utzoo!attcan!uunet!lll-winken!lll-tis!helios.ee.lbl.gov!pasteur!ames!lamaster
From: lamaster@ames.arc.nasa.gov (Hugh LaMaster)
Newsgroups: comp.arch
Subject: Re: RISC v. CISC (was The NeXT problem)
Message-ID: <17207@ames.arc.nasa.gov>
Date: 27 Oct 88 21:06:39 GMT
References: <156@gloom.UUCP> <310@lynx.zyx.SE> <332@pvab.UUCP> <10447@cup.portal.com>
Reply-To: lamaster@ames.arc.nasa.gov.UUCP (Hugh LaMaster)
Organization: NASA Ames Research Center, Moffett Field, Calif.
Lines: 25

In article <10447@cup.portal.com> bcase@cup.portal.com (Brian bcase Case) writes:
>>The more registers, the more to save at every context switch in a typical
:
>What data do you have to substantiate this claim?  This is another popular
>misconception, I think.

(Interesting data on Pyramid study omitted)

>which is 0.20 percent of the total available CPU time.  I don't think
>this is significant.  For some implmentations, it is more like 1 cycle

I agree with this point and would like to add that there may be some
simple things which can be added to hardware to speed up context
switching.  CDC has typically used a "save everything" approach with
the complete save taking place with a single hardware instruction.
This instruction is easy to implement in a RISC machine as well, and it
trades some use of extra memory bandwidth but with a potential payoff
in less code executed to do a context switch.  However, it may be true
that picking the next runnable process may dominate by far the cost of
a context switch.  Is there any hard data out there?

-- 
  Hugh LaMaster, m/s 233-9,  UUCP ames!lamaster
  NASA Ames Research Center  ARPA lamaster@ames.arc.nasa.gov
  Moffett Field, CA 94035     
  Phone:  (415)694-6117