Path: utzoo!utgpu!water!watmath!clyde!att!osu-cis!tut.cis.ohio-state.edu!ukma!uflorida!beach.cis.ufl.edu!cl0
From: cl0@beach.cis.ufl.edu (Chi-Chou Lin)
Newsgroups: comp.arch
Subject: Multiprocessor RISC
Message-ID: <18894@uflorida.cis.ufl.EDU>
Date: 31 Oct 88 08:29:21 GMT
Sender: news@uflorida.cis.ufl.EDU
Reply-To: cl0@beach.cis.ufl.edu ()
Organization: UF CIS Department
Lines: 23



Ok, so much for the RISC vs. CISC. How about change to another
topic:
	What would be the features you would add to RISC-like
	architecture to support OS (either uniprocessor or
	multiprocessor) functions? Consider the issues of cost,
	efficiency, flexibility, and other "RISCy" issue. How
	to justify?

Another issue is :
	Is there any differences between RISC and CISC to
	support a multiprocessor system?

Currently I only know the SPUR architecture at Berkeley is a
multiprocessor RISC (any else?). SPUR has a large cache and
instruction prefetch buffer for each processor. These features
already exist in CISC for a long time. So I wonder if there is
any features necessary to support a RISC multiprocessor
system, but these features don't exist in a CISC multiprocessor
system.

cl0@beach.cis.ufl.edu