Path: utzoo!yunexus!geac!syntron!jtsv16!uunet!portal!cup.portal.com!bcase
From: bcase@cup.portal.com (Brian bcase Case)
Newsgroups: comp.arch
Subject: Re: Longer load/store because of register windows
Message-ID: <10639@cup.portal.com>
Date: 29 Oct 88 21:51:08 GMT
Article-I.D.: cup.10639
References: <156@gloom.UUCP> <310@lynx.zyx.SE> <332@pvab.UUCP> <15964@agate
Organization: The Portal System (TM)
Lines: 22

>I don't know enough of the details to know why this is so, but I have been
>told that "all other things being equal" (i.e. a typical processor design
>with typical technology) that it is difficult to provide more than about
>32 registers with single cycle read/write access.

Wow, I don't know who told you this, but it is not true for VLSI
implementations.  Creating a register file from discrete memory chips
is *much* harder (I did it once in ECL; try it with two write ports!).
In VLSI, the register file is typically implemented in a write-before-
read fashion; so in some sense, the register file is doing two accesses
per cycle.  I.e., register file read must take less than 1/2 cycle
(pipeline register set-up time, some clock margin, etc.).

WRT the discussion about variable-sized windows, the 29K allows (doesn't
force) activation records (stack frames) to be allocated in the local
register file (this is what windowing means).  These activation records
are variable-sized windows, with resolution of one register, up to
the size of the local register file (128 registers).  The "stack-pointer-
plus-offset" calculation is overlapped with the register file write
operation (write-before read).

The register file can also be used as a flat space of 128 registers.