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From: lindsay@k.gp.cs.cmu.edu (Donald Lindsay)
Newsgroups: comp.arch
Subject: Re: ETA-10: CMOS or ECL?
Keywords: ETA-10
Message-ID: <3453@pt.cs.cmu.edu>
Date: 30 Oct 88 18:54:32 GMT
Article-I.D.: pt.3453
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Organization: Carnegie-Mellon University, CS/RI
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My file system turned up 
"A Cryogenically Cooled CMOS VLSI Supercomputer"
VLSI Systems Design, June 1987

Some highlights:
3,000,000 circuits per CPU, on 240 gate arrays on one board
gate arrays have 284 pins (surface mount TAB) with 11-mil-center leads;
   1.25 micron; 20k gates max; 2nd sourced (Honeywell & Performance Semi)
electronic clock tuning on each chip, so all chips are within 100 pico
   of each other
6 pins/chip dedicated to self-test: everyone should be so smart.
The board is 17" x 23", 20 signal layers, 40 layers total.
Their CMOS is 1.6 times faster at liquid nitrogen temperatures.  (Both N
and P devices improve the same amount, so there aren't skew problems.)
Plus, the metallization is six times less resistive, which improves any
RC delays. (Plus lower noise, which I assume they can't count on, since
the machine has to also work at ambient.)

On the other hand, the Crays are faster. The Great White Hope at ETA is
that they will learn how to roll these things out like cookies and 
then the customers will spring for multiprocessors.

- plus the inevitable chip shrink -
-- 
Don		lindsay@k.gp.cs.cmu.edu    CMU Computer Science