Path: utzoo!yunexus!geac!syntron!jtsv16!uunet!lll-winken!lll-lcc!ames!pasteur!ucbvax!hplabs!otter!kers
From: kers@otter.hple.hp.com (Christopher Dollin)
Newsgroups: comp.arch
Subject: Re: RISC vs CISC
Message-ID: <780010@otter.hple.hp.com>
Date: 31 Oct 88 08:53:41 GMT
Article-I.D.: otter.780010
References: <1213@dutesta.UUCP>
Organization: Hewlett-Packard Laboratories, Bristol, UK.
Lines: 49

Some remarks about the ARM, following Brian Case's response to the basenote. I
speak solely as an owner of an Acorn Archimedes with some experience in
compiler writing; my employers won't buy me one for my desk [are you
surprised?]

| Its biggest problems are implementation and support.  The address bus is
| only 26 bits, faulting handing and memory management are a totally

Memory management is not part of the chip, but has to be provided by an
external memory manager. The current version of this (MEMC) does seem to be
a little odd, but then, I'm not really familiar with MMU devices.

| weird, very fast implementations do not exist, no one is providing
| comprehensive support (maybe VLSI tech is doing a better job these days,
| but where are the compilers?  UNIX implementations?  etc.), etc.  If I

Acorn a *supposed* to be working on a Unix implementation. Last I heard it was
die out toward the end of this year. Silence is golden ....

| remember correctly, it also has only 25, or some weird number of, registers,
| and only some are available to user code.

25 on-chip registers. Each operating mode sees 16; in the three non-user
modes, some of the user registers are shadowed out; in SVC and MI (maskable
interupt) mode, the R15 (PC) and R14 (return link) are shadowed, and in NMI
(non-MI) mode, R11-R15 are shadowed. This is to allow fast context switching,
especially in NMI code (where the NMI owner can set up the NMI registers and
return to user code; NMIs can then operate with *no* register save-restore).
Acorn operating systems are *heavily* interrupt-driven.

| One of them is the PC, which is not good for really high-performance
| implementations.  The ALU and SH instructions take 2 cycles.

No, one cycle. An ALU instuction with one operand shifted *by an amount held
in a register* takes an additional cycle. Incidentally, one should be careful
and distinguish *sequential* cycles from *non-sequential* cycles, as the
instruction fetch is in burst mode (I think that's the right term).

| It has only an address bus and a combined data/instruction bus.  For best
| performance, you need more bandwidth. At high clock rates, the bus protocols
| will not work. I have seen small graphics kernels on which the ARM does better
| than any vanilla RISC in terms of cycle count.  But vanilla RISCs win in total
| time (shorter cycle).  Most of the implementation problems could be solved,
| but who is solving them?

Well, presumably Acorn. If not, I can imagine I'll be very upset in a few
years time ....

Regards, Kers.
"If anything anyone lacks, they'll find it all ready in stacks."