Newsgroups: comp.arch
Path: utzoo!henry
From: henry@utzoo.uucp (Henry Spencer)
Subject: Re: RISC v. CISC --more misconceptions
Message-ID: <1988Nov3.185535.28850@utzoo.uucp>
Organization: U of Toronto Zoology
References: <156@gloom.UUCP> <18931@apple.Apple.COM> <40@sopwith.UUCP> <10471@s.ms.uky.edu> <611@quintus.UUCP>
Date: Thu, 3 Nov 88 18:55:35 GMT

In article <611@quintus.UUCP> ok@quintus.UUCP (Richard A. O'Keefe) writes:
>But it _has_ been tossed out of many designs:  the IBM RT PC (at any
>rate the old ones) had no floating-point instructions, but used a
>National chip (32081?).

I.e., it had floating-point hardware.  Why do you say that floating
point was "tossed out" of its design??

>The AMD 29000 manual says that floating-point
>ops are currently extracodes emulated by a trap handler...

Which may well use the 29xyz (don't remember the number offhand) chip
to do all the real work.  Again, it hasn't been tossed out, just moved
around a bit.

>And of course
>there are all the 680x0, 320xx, 80*86 and so on, with floating-point
>done by a co-processor.

So?  On most of those chips, the software can't tell the difference.
Does the FP hardware have to be on the CPU chip to be "real" somehow?
Why?
-- 
The Earth is our mother.        |    Henry Spencer at U of Toronto Zoology
Our nine months are up.         |uunet!attcan!utzoo!henry henry@zoo.toronto.edu