Path: utzoo!attcan!uunet!lll-winken!lll-tis!helios.ee.lbl.gov!pasteur!ucbvax!hplabs!otter!kers
From: kers@otter.hple.hp.com (Christopher Dollin)
Newsgroups: comp.arch
Subject: Re: Re: ARM (was RISC vs CISC)
Message-ID: <780012@otter.hple.hp.com>
Date: 2 Nov 88 08:42:24 GMT
References: <75457@sun.uucp>
Organization: Hewlett-Packard Laboratories, Bristol, UK.
Lines: 17

David DiGiacomo says (referring to the ARM):

| One bizarre thing about the architecture is the lack of 16 bit load/store
| instructions.  I imagine this would add some excitement to writing a C
| compiler.

One interesting thing reported in the ARM assembler book is the behaviour of
the ARM on non-aligned word loads. The word with (address &~ 3) is loaded and
rotated so that the low-order stuff is in the correct position. Thus you can
load a half-word (assuming it's aligned on a half-word boundary) with one
load and a mask operation.

The book doesn't say if the same happens on store. And I haven't tried it
out - yet. Whn I can afford the C compiler, or meet the guys who wrote it, I'll
find out what *they* do.

Regards,    | "See the darkness all around
Kers.       | Is coming down on you ..."