Path: utzoo!attcan!uunet!lll-winken!lll-tis!ames!mailrus!uflorida!haven!rutgers!rochester!pt.cs.cmu.edu!a.gp.cs.cmu.edu!koopman
From: koopman@a.gp.cs.cmu.edu (Philip Koopman)
Newsgroups: comp.arch
Subject: Re: Multiprocessor RISC
Summary: Memory Bandwidth!!
Message-ID: <3468@pt.cs.cmu.edu>
Date: 2 Nov 88 16:49:25 GMT
References: <18894@uflorida.cis.ufl.EDU>
Sender: netnews@pt.cs.cmu.edu
Organization: Carnegie-Mellon University, CS/RI
Lines: 17

In article <18894@uflorida.cis.ufl.EDU>, cl0@beach.cis.ufl.edu (Chi-Chou Lin) writes:
............ 
> Another issue is :
> 	Is there any differences between RISC and CISC to
> 	support a multiprocessor system?

Memory Bandwidth problems!  If you are using a shared memory model,
memory bandwidth is often the limiting factor to how many processors
you can put into the system.  RISC processors need a lot more
memory bandwidth at the CPU chip than CISC processors.
That means a RISC multiprocessor has to be a lot more careful about
getting good cache hit rates across a wide range of software execution
profiles to avoid saturating the system bus.

  Phil Koopman                koopman@maxwell.ece.cmu.edu   Arpanet
  5551 Beacon St.
  Pittsburgh, PA  15217    
PhD student at CMU and sometime consultant to Harris Semiconductor.