Path: utzoo!attcan!uunet!seismo!sundc!pitstop!sun!chiba!khb
From: khb%chiba@Sun.COM (Keith Bierman - Sun Tactical Engineering)
Newsgroups: comp.arch
Subject: Re: RISC v. CISC
Message-ID: <75926@sun.uucp>
Date: 3 Nov 88 01:08:48 GMT
References: <156@gloom.UUCP> <6865@winchester.mips.COM> <3264@newton.praxis.co.uk>
Sender: news@sun.uucp
Reply-To: khb@sun.UUCP (Keith Bierman - Sun Tactical Engineering)
Organization: Sun Microsystems, Mountain View
Lines: 25

In article <3264@newton.praxis.co.uk> mph@praxis.co.uk (Martin Hanley) writes:
>
>With the Acorn RISC Machine (ARM), *EVERY* instruction can be
>conditional, not just the jumps. If the condition flags are not set,
>then the instruction is ignored. Also, a bit in the instruction flags
>whether of not to reset the condition codes when executing the
>instruction.
>
>This setup has obvious advantages when it comes to preserving
>pipelines, since the major bugbear of said pipelines is that every
>jump causes them to be broken. This is circumvented to some extent by
>the provision of delayed jumps (which the ARM also has), but not
>entirely.
>
>Does any other machine have this feature? Anybody have comments on it?

The late Cydra 5 had 'em. The condition bits could (and often were)
set based on the data (thus the name "directed dataflow"). Since the
cydra 5 had multiple instructions (6/7 depending on who counted) per
clock, and very long pipes (26 for memory fetch) these conditional
exeuction features were very valuable.


Keith H. Bierman
It's Not My Fault ---- I Voted for Bill & Opus