Path: utzoo!utgpu!attcan!uunet!portal!cup.portal.com!bcase
From: bcase@cup.portal.com (Brian bcase Case)
Newsgroups: comp.arch
Subject: Re: A simple question on RISC
Message-ID: <10802@cup.portal.com>
Date: 3 Nov 88 01:48:30 GMT
References: <6544@xanth.cs.odu.edu> <75577@sun.uucp>
Organization: The Portal System (TM)
Lines: 30

>RISC == reduced instruction 

That's reduced instruction set computer.

>Thus was born RISC. If we ignore Seymour (always a mistake), the early
>RISC prople were IBM, UCB and Stanford. With the exception of Seymour,
>all of these early RISC machines were too simple.

Just to put in my 2 cents, not everyone (e.g., me) agrees that Seymour
builds RISC machines.  They might be simple, but they are not RISCs, by
my estimation.

As I understand it, the MIPS guys concluded that the early Stanford MIPS
architecture was too *complicated*, not too simple (the packing of one
or two instructions per word really complicated the pipeline control, at
least that's what I remember reading, and some instructions were two-
address while others were three).  The 801 had a very complex register
file (3 reads, two writes).  Subsequent machines seem to be simpler
(although we might all be surprised by John Cocke's Americas machine.).

Notice also that Seymour's first machine came out in '76 (I believe).
The 801 research began in 1975, though it was perhaps not as focused
as it later became.  I'd say this is a pretty close call to who was first.
The 801 guys set down the ground rules and then let the compiler guys
define the instructions.  I don't think this is the way Seymour did it.
Seymour is a smart guy and understands what can go fast and what cannot,
but little things like the lack of three-address integer instructions
shows that he was not designing from the point of view of a compiler
guy.  And the Multiflow VLIW and Wulf's WM machine are closer to RISC
vector machines than are the Crays.