Path: utzoo!utgpu!attcan!uunet!yale!mfci!colwell
From: colwell@mfci.UUCP (Robert Colwell)
Newsgroups: comp.arch
Subject: Re: A simple question on RISC
Message-ID: <547@m3.mfci.UUCP>
Date: 4 Nov 88 13:48:52 GMT
References: <6544@xanth.cs.odu.edu> <75577@sun.uucp> <10802@cup.portal.com> <76083@sun.uucp>
Sender: colwell@mfci.UUCP
Reply-To: colwell@mfci.UUCP (Robert Colwell)
Organization: Multiflow Computer Inc., Branford Ct. 06405
Lines: 50

In article <76083@sun.uucp> khb@sun.UUCP (Keith Bierman - Sun Tactical Engineering) writes:
>In article <10802@cup.portal.com> bcase@cup.portal.com (Brian bcase Case) writes:
>
>>The 801 had a very complex register
>>file (3 reads, two writes).

Maybe this is due to all the hair they added on behalf of their step-multiply
and divide; this is one of the RISC patents.  Apparently, they can interrupt
on some of the bits in the register file.

>>The 801 research began in 1975, though it was perhaps not as focused
>>as it later became.  I'd say this is a pretty close call to who was first.

I was at one of Patterson's first RISC talks at Bell Labs in late '79
or early '80.  I recall him giving credit to John Cocke directly (then)
as to how he got involved with RISC.  I don't know how Hennessy got
involved, and never thought to ask him.

>>The 801 guys set down the ground rules and then let the compiler guys
>>define the instructions.  I don't think this is the way Seymour did it.
>>Seymour is a smart guy and understands what can go fast and what cannot,
>>but little things like the lack of three-address integer instructions
>>shows that he was not designing from the point of view of a compiler
>>guy.  And the Multiflow VLIW and Wulf's WM machine are closer to RISC
>>vector machines than are the Crays.
>
>True on both counts. Seymour designs simple things which go fast. He
>assumes that compiler writers can cope. This is, perhaps, not the best
>approach...but his track record is pretty good (CDC owned the high
>performance computer market during his long reign). The Multiflow and
>Cydra machines are, arguably, RISC's .

I agree; calling a Cray a RISC is (to my mind) more palatable than 
linking lots of registers to RISCs, but not by that much.

I like discussing our VLIW in the RISC context, because I think it
demonstrates the important RISC principles beautifully (smart compilers,
simple hardware (that's what our software people think, anyway), exposed
pipelines, load/store, no microcode).  But!! -- the instruction word
can be 512 bits long in our largest announced machine.  2**512 is a
lot of instructions.  And yes, I'm being a bit mischievous, too,
because any one functional unit's instruction set is small enough
to need only the simplest hardware for decode.  The rest of the control
hardware is to handle the self-draining pipelines, a design decision
that (I think) was the correct one, even for a RISC machine.

Bob Colwell            mfci!colwell@uunet.uucp
Multiflow Computer
175 N. Main St.
Branford, CT 06405     203-488-6090