Path: utzoo!utgpu!attcan!uunet!husc6!uwvax!rutgers!att!mtuxo!mtgzz!drutx!druhi!cosmos
From: cosmos@druhi.ATT.COM (Ronald A. Guest)
Newsgroups: comp.arch
Subject: Re: Multiprocessor RISC
Message-ID: <3701@druhi.ATT.COM>
Date: 3 Nov 88 15:05:03 GMT
References: <18894@uflorida.cis.ufl.EDU> <3468@pt.cs.cmu.edu>
Organization: AT&T, Denver, CO
Lines: 19

In article <3468@pt.cs.cmu.edu>, koopman@a.gp.cs.cmu.edu (Philip Koopman) writes:
> you can put into the system.  RISC processors need a lot more
> memory bandwidth at the CPU chip than CISC processors.

You are right in saying that RISC CPUs generate lots of references very
quickly, and memory bandwidth is certainly a key to tightly coupled
multiprocessors.  However, I have not observed any significant difference
between high performance CISC micros and high performance RISC micros in
sensitivity to memory bandwidth.  High performance CISCs we have tested
depend just as heavily on caches as the RISCs do, since the RISCs seem to
have an inherently higher cache hit rate.  The CISCs seem to have lower hit
rates so it appears to end up being a wash.  The only exception I could see
is a workstation type system with only a small memory need that could be met
by a limited amount of on board RAM and no 'real' memory bus.  Of course,
then it also couldn't be a tightly coupled multiprocessor.

Ronald A. Guest, Supervisor     cosmos@druhi.ATT.COM  or  att!druhi!cosmos
AT&T Bell Laboratories          <--- but these are my thoughts, not theirs
12110 N. Pecos St.              Denver, Colorado 80234          (303) 538-4896