Path: utzoo!attcan!uunet!lll-winken!ubvax!vsi1!apple!baum
From: baum@Apple.COM (Allen J. Baum)
Newsgroups: comp.arch
Subject: Re: A simple question on RISC
Message-ID: <19988@apple.Apple.COM>
Date: 4 Nov 88 23:38:13 GMT
References: <6544@xanth.cs.odu.edu> <75577@sun.uucp> <10802@cup.portal.com> <76083@sun.uucp> <547@m3.mfci.UUCP>
Reply-To: baum@apple.UUCP (Allen Baum)
Organization: Apple Computer, Inc.
Lines: 18

[]
>In article <547@m3.mfci.UUCP> colwell@mfci.UUCP (Robert Colwell) writes:
>>>The 801 had a very complex register
>>>file (3 reads, two writes).
>
>Maybe this is due to all the hair they added on behalf of their step-multiply
>and divide; this is one of the RISC patents.  Apparently, they can interrupt
>on some of the bits in the register file.

Actually--
 3 reads - required for indexed store (RegA-> Mem(RegB+RegX)
 2 writes- required for delayed loads (load RgA in cyc 1, stores in cyc 2 along
                                       with whatever else is executed in cyc 2)

Um, about interrupting on some of the bits in the register file- I don't recall
seeing that in the patents. Do you have a reference?
--
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