Path: utzoo!attcan!uunet!husc6!mailrus!purdue!decwrl!sgi!jmb@patton.SGI.COM
From: jmb@patton.SGI.COM (Jim Barton)
Newsgroups: comp.arch
Subject: Re: Multiprocessor RISC
Summary: Very out of date
Message-ID: <21690@sgi.SGI.COM>
Date: 5 Nov 88 17:35:28 GMT
References: <18894@uflorida.cis.ufl.EDU>
Sender: daemon@sgi.SGI.COM
Organization: Silicon Graphics, Inc., Mountain View, CA
Lines: 34

In article <18894@uflorida.cis.ufl.EDU>, cl0@beach.cis.ufl.edu (Chi-Chou Lin) writes:
> 
   ...
> 
> Currently I only know the SPUR architecture at Berkeley is a
> multiprocessor RISC (any else?). SPUR has a large cache and
> instruction prefetch buffer for each processor. These features
> already exist in CISC for a long time. So I wonder if there is
> any features necessary to support a RISC multiprocessor
> system, but these features don't exist in a CISC multiprocessor
> system.
> 
> cl0@beach.cis.ufl.edu

Have you been living in an igloo for the past year?  There are several
commerically available RISC based multiprocessors on the market today.
Consider the Ardent Titan (MIPS R2000), Apollo DN10000 (PRISM) and
the SGI POWERSeries (MIPS R2000 and R3000).

The minimum necessary hardware in each seems to be coherent caches, but
each has tweaks in other areas.  A RISC multiprocessor is not any harder
than any other kind of multiprocessor, so it should not be viewed as
unique when considering multiprocessor problems and solutions.  The
harder aspects are simply the faster parts and larger caches needed
when dealing with faster (RISC based) processors.


-- Jim Barton
Silicon Graphics Computer Systems    "UNIX: Live Free Or Die!"
jmb@sgi.sgi.com, sgi!jmb@decwrl.dec.com, ...{decwrl,sun}!sgi!jmb

  "I used to be disgusted, now I'm just amused."
			- Elvis Costello, 'Red Shoes'
--