Path: utzoo!attcan!uunet!mfci!colwell
From: colwell@mfci.UUCP (Robert Colwell)
Newsgroups: comp.arch
Subject: Re: A simple question on RISC
Message-ID: <551@m3.mfci.UUCP>
Date: 6 Nov 88 02:21:14 GMT
References: <6544@xanth.cs.odu.edu> <75577@sun.uucp> <10802@cup.portal.com> <76083@sun.uucp> <547@m3.mfci.UUCP> <19988@apple.Apple.COM>
Sender: colwell@mfci.UUCP
Reply-To: colwell@mfci.UUCP (Robert Colwell)
Organization: Multiflow Computer Inc., Branford Ct. 06405
Lines: 32

>>In article <547@m3.mfci.UUCP> colwell@mfci.UUCP (Robert Colwell) writes:
>>>>The 801 had a very complex register
>>>>file (3 reads, two writes).
>>
>>Maybe this is due to all the hair they added on behalf of their step-multiply
>>and divide; this is one of the RISC patents.  Apparently, they can interrupt
>>on some of the bits in the register file.
>
>Actually--
> 3 reads - required for indexed store (RegA-> Mem(RegB+RegX)
> 2 writes- required for delayed loads (load RgA in cyc 1, stores in cyc 2 along
>                                       with whatever else is executed in cyc 2)
>
>Um, about interrupting on some of the bits in the register file- I don't recall
>seeing that in the patents. Do you have a reference?

I was confusing two separate patents.  The first, related to the 801,
was on their condition code register, which collected bits from all
over the place.  You could interrupt on them, and this register could
also be transferred to the general registers, manipulated, and written
back.  (patent 4,589,087)

The one I was mixing it up with is 4,630,195, which is evidently not
related to the 801 at all, and concerns tagging the general registers
such that overlapping transfers are properly interlocked.

Thus proving once again that I can't read legalese worth a darn.

Bob Colwell            mfci!colwell@uunet.uucp
Multiflow Computer
175 N. Main St.
Branford, CT 06405     203-488-6090