Path: utzoo!attcan!uunet!portal!cup.portal.com!bcase
From: bcase@cup.portal.com (Brian bcase Case)
Newsgroups: comp.arch
Subject: Re: A simple question on RISC
Message-ID: <10938@cup.portal.com>
Date: 5 Nov 88 21:08:39 GMT
References: <6544@xanth.cs.odu.edu> <75577@sun.uucp> <10802@cup.portal.com>
Organization: The Portal System (TM)
Lines: 14

>Actually--
> 3 reads - required for indexed store (RegA-> Mem(RegB+RegX)
> 2 writes- required for delayed loads (load RgA in cyc 1, stores in cyc 2 along
>                                       with whatever else is executed in cyc 2)

Well, two write ports are not required to handle one outstanding load; the
29K has a patented mechanism for buffering the load result in a separate
latch and then forwarding from there into the data path until an instruction
that creates a register-write hole (e.g. jump, store) comes along.  Notice
also that the next load always creates an opportunity to write back the
previously loaded valued:  the newly loaded data is first destined for the
latch anyway, so whatever is already in the latch can use the writeback stage
of the outgoing load.  This is the brilliant invention, I wish I were the
inventor!  (A once-again Danish citizen named Ole Moller thought of it.)