Newsgroups: comp.arch
Path: utzoo!henry
From: henry@utzoo.uucp (Henry Spencer)
Subject: Re: Comiplers for RISC v. CISC
Message-ID: <1988Nov7.180739.15757@utzoo.uucp>
Organization: U of Toronto Zoology
References: <156@gloom.UUCP> <890@cps3xx.UUCP> <10194@cup.portal.com> <10722@cup.portal.com> <7832@bloom-beacon.MIT.EDU>
Date: Mon, 7 Nov 88 18:07:39 GMT

In article <7832@bloom-beacon.MIT.EDU> tada@athena.mit.edu (Michael Zehr) writes:
>A "simple" machine?  To use RISC to it's full benefit you have to try and
>cut CPU to memory data exchange, keep piplines well-filled, probably try 
>to keep memory references in burst to increase cache hit rate.  

Precisely the same is true of CISCs, and the much greater complexity of
the machine makes it harder to predict the effects of these factors.
Do *you* know how to keep pipelines well-filled or cache hit rate up
on a VAX 8600?  Does anybody?  I sure don't.  On a 29000 or a MIPS chip,
it's not that hard to figure out.
-- 
The Earth is our mother.        |    Henry Spencer at U of Toronto Zoology
Our nine months are up.         |uunet!attcan!utzoo!henry henry@zoo.toronto.edu