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From: kyriazis@rpics (George Kyriazis)
Newsgroups: comp.arch
Subject: Re: A simple question on RISC
Message-ID: <1618@imagine.PAWL.RPI.EDU>
Date: 1 Nov 88 15:35:20 GMT
References: <6544@xanth.cs.odu.edu> <75577@sun.uucp>
Sender: news@imagine.PAWL.RPI.EDU
Reply-To: kyriazis@turing.cs.rpi.edu (George Kyriazis)
Organization: RPI CS Dept.
Lines: 26

In article <75577@sun.uucp> khb@sun.UUCP (Keith Bierman - Sun Tactical Engineering) writes:
>
>After a few years, some bright people noticed what Seymour Cray never
>forgot, hardwired logic was faster. Also that maybe not all those
>nifty wizbang instructions ever got used. Or if they got used, it was
>so rare that it didn't matter. Or they got used, and it was slower
>than some combination of simple instructions. Or all of the above.
>
>Thus was born RISC....
>

One small detail that I remember reading in the thesis concerning the
RISC II chip.  If one instruction, is not used very often, it not only
takes up silicon space, but also slows down the rest decoding circuitry,
since it adds output capacitance (in the case of MOS) to the previous
gate level.  The elimination of one signle instruction won't do much good,
but if you do that systimatically and organize the decoding logic so
it has a minumum level of levels and minimum input capacitance, you score.
(Remember the input capacitance of the decoding circuitry is the output
capacitance of the spevious stage (simplification), namely the instruction
register.


  George Kyriazis
  kyriazis@turing.cs.rpi.edu
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