Path: utzoo!utgpu!attcan!uunet!lll-winken!lll-tis!helios.ee.lbl.gov!pasteur!agate!bionet!apple!baum
From: baum@Apple.COM (Allen J. Baum)
Newsgroups: comp.arch
Subject: Re: A simple question on RISC
Message-ID: <20141@apple.Apple.COM>
Date: 7 Nov 88 22:51:44 GMT
References: <6544@xanth.cs.odu.edu> <75577@sun.uucp> <10802@cup.portal.com> <10938@cup.portal.com>
Reply-To: baum@apple.UUCP (Allen Baum)
Organization: Apple Computer, Inc.
Lines: 22

[]
>In article <10938@cup.portal.com> bcase@cup.portal.com (Brian bcase Case) writes:
>>Actually--
>> 3 reads - req'd for indexed store (RegA-> Mem(RegB+RegX)
>> 2 writes- req'd for delayed loads (load RgA in cyc 1, stores in cyc 2 along
>>                                   with whatever else is executed in cyc 2)
>
>Well, two write ports are not required to handle one outstanding load; the
>29K has a patented mechanism for buffering the load result in a separate
>latch and then forwarding from there into the data path until an instruction
>that creates a register-write hole (e.g. jump, store) comes along.  Notice
>also that the next load always creates an opportunity to write back the
>previously loaded valued:  the newly loaded data is first destined for the
>latch anyway, so whatever is already in the latch can use the writeback stage
>of the outgoing load.  This is the brilliant invention, I wish I were the
>inventor!  (A once-again Danish citizen named Ole Moller thought of it.)

I don't know if the original 801 had autoincrmenting addressing modes, but
that in itself is enough to require a two write-port reg. file.

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