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From: cjosta@taux01.UUCP (Jonathan Sweedler)
Newsgroups: comp.arch
Subject: Re: Lisp "future" instruction in 88k hardware.
Message-ID: <917@taux01.UUCP>
Date: 8 Nov 88 06:13:52 GMT
References: <7472@winchester.mips.COM| <3385@geaclib.UUCP|
Reply-To: cjosta@taux01.UUCP (Jonathan Sweedler)
Organization: National Semiconductor (Israel) Ltd.
Lines: 36

In article <3385@geaclib.UUCP| daveb@geaclib.UUCP (David Collier-Brown) writes:
|From article <7472@winchester.mips.COM|, by cprice@mips.COM (Charlie Price):
|| From the architecture spec:
|| 
||   After a multiply or divide operation
||   is started, execution of other instructions may continue in parallel.
||   The MFHI and MFLO instructions are
||   interlocked so that any attempt to read them before operations
||   have completed will cause execution of instructions to be delayed
||   until the operations finishes.
|
|  Some of you may recognize this set of behavior as substantially
|identical to the "future" function in experimental lisp(s):
|  Future takes a computation and returns a function which, when
|called later will do one of:
|	1) return the result immediately, because it has been computed
|	   concurrently and the computation has completed, or
|	2) block until the concurrent computation is finished, or
|	3) compute it itself if it could do it concurrently.
|
|  The significance of this should be apparent: here is a RISC
|instruction which can be decomposed into two, independently useful
|instructions:
|	1) floating accumulator move (of course)
|	2) wait for concurrent computation to complete...
|

Isn't this the same principle as scoreboarding in a pipelined
architecture that is used in many processors today?  In such a design,
an instruction is put in the pipe, but if another instruction tries to
read the destination register of the first instruction before the
result is written into the register, then the pipe is stalled.
Am I missing something?
-- 
Jonathan Sweedler  ===  National Semiconductor Israel
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