Path: utzoo!attcan!uunet!ncrlnk!ncr-sd!hp-sdd!hplabs!hpl-opus!hpccc!hp-sde!wunder
From: wunder@hp-sde.SDE.HP.COM (Walter Underwood)
Newsgroups: comp.arch
Subject: Re: Lisp "future" instruction in 88k hardware.
Message-ID: <580004@hp-sde.SDE.HP.COM>
Date: 8 Nov 88 01:54:20 GMT
References: <3385@geaclib.UUCP>
Organization: HP Software Dev Environments - Palo Alto, CA
Lines: 35


   >   implementation-dependent.  The MFHI and MFLO instructions are
   >   interlocked so that any attempt to read them before operations
   >   have completed will cause execution of instructions to be delayed
   >   until the operations finishes.

     Some of you may recognize this set of behavior as substantially
   identical to the "future" function in experimental lisp(s):

   ...

     The significance of this should be apparent: here is a RISC
   instruction which can be decomposed into two, independently useful
   instructions:
	   1) floating accumulator move (of course)
	   2) wait for concurrent computation to complete...

As an ALU implementation, this technique dates from the CDC 6600.  In
that machine, even loads from memory were done that way -- stuff the
address of the desired location in a register, and some time later,
the data shows up in a corresponding register.  Machines were
outfitted with a few add and multiply units, so that several
operations could be overlapped.  With careful coding, you could
get a lot of computation done in a short time.

No surprise that DEC advertised the VAX-11/780 as "half the speed of a
CDC 6600 for floating point" at a time when the 6600 was a 15 year old
machine (1978).

You can find a nice description of the CDC 6600 in Bell and Newell,
"Computer Structures: Readings and Examples".  The article is probably
in the revised version of that book (Siewiorek, Bell, and Newell) as
well, but I only have the original.

wunder