Path: utzoo!attcan!uunet!cbmvax!daveh
From: daveh@cbmvax.UUCP (Dave Haynie)
Newsgroups: comp.arch
Subject: Re: HW v. SW (was RISC v. CISC --more misconceptions)
Message-ID: <5195@cbmvax.UUCP>
Date: 8 Nov 88 16:18:29 GMT
References: <866@cernvax.UUCP>
Organization: Commodore Technology, West Chester, PA
Lines: 23

in article <866@cernvax.UUCP>, hjm@cernvax.UUCP (Hubert Matthews) says:

> The INMOS T800 has an instruction bitrevword, which turns a
> little-endian word into a big-endian word, effectively doing a
> reflection in the middle.  Great for FFT shuffle routines.  In
> software, it takes quite some time.  In hardware it takes just over 
> 1 microsecond on a 30MHz part.  

That's 30 cycles, which would be 30 instructions for a true instruction/cycle 
RISC machine.  The claim for the very simple ARM machine was something like 5 
instructions, which would total 10 cycles if the quoted 1.9 cycles per 
instruction is reasonable (and you'd of course have to imagine a 30MHz ARM
machine).  If a baby RISC machines does this 3x more efficiently than the
Transputer's hardwired instruction, I'd certainly expect a more grown-up 
RISC chip like a MIPS or 88K to do better.  I believe there are arguments for
implementing operations, even complex ones, in hardware.  This ain't one of
'em.

> 	Hubert Matthews
-- 
Dave Haynie  "The 32 Bit Guy"     Commodore-Amiga  "The Crew That Never Rests"
   {uunet|pyramid|rutgers}!cbmvax!daveh      PLINK: D-DAVE H     BIX: hazy
              Amiga -- It's not just a job, it's an obsession