Path: utzoo!utgpu!watmath!clyde!bellcore!rutgers!mit-eddie!bu-cs!purdue!decwrl!sun!pitstop!sundc!seismo!uunet!mcvax!ukc!stl!stc!praxis!gauss!mph
From: mph@praxis.co.uk (Martin Hanley)
Newsgroups: comp.arch
Subject: Re: RISC v. CISC
Message-ID: <3264@newton.praxis.co.uk>
Date: 1 Nov 88 11:43:47 GMT
References: <156@gloom.UUCP> <6865@winchester.mips.COM>
Sender: news@praxis.co.uk
Reply-To: mph@praxis.co.uk (Martin Hanley)
Organization: Praxis Systems plc, Bath, UK
Lines: 24


With the Acorn RISC Machine (ARM), *EVERY* instruction can be
conditional, not just the jumps. If the condition flags are not set,
then the instruction is ignored. Also, a bit in the instruction flags
whether of not to reset the condition codes when executing the
instruction.

This setup has obvious advantages when it comes to preserving
pipelines, since the major bugbear of said pipelines is that every
jump causes them to be broken. This is circumvented to some extent by
the provision of delayed jumps (which the ARM also has), but not
entirely.

Does any other machine have this feature? Anybody have comments on it?

							mph.

-----------------------------------------------------------------------------
"I'm not a god, I was misquoted"   - Lister, Red Dwarf

These are, of course, my opinions. Who else would want them?

My home:      mph@praxis.co.uk
-----------------------------------------------------------------------------