Path: utzoo!utgpu!watmath!clyde!mcdchg!chinet!att!osu-cis!tut.cis.ohio-state.edu!bloom-beacon!bu-cs!purdue!decwrl!sun!pitstop!sundc!seismo!uunet!portal!cup.portal.com!bcase
From: bcase@cup.portal.com (Brian bcase Case)
Newsgroups: comp.arch
Subject: Re: RISC vs CISC
Message-ID: <10606@cup.portal.com>
Date: 28 Oct 88 20:00:39 GMT
References: <1213@dutesta.UUCP>
Organization: The Portal System (TM)
Lines: 34

>Am I the only one who ever heard about the Acorn Risc chip and there computer
>'Archimedes', or do all of you ignore this machine just because it is a
>small (british) company which manufactures strange computers (BBC).
>I do not own an Archimedes, but I like the machine -> it is cheap, fast,
>Hi-res lots of memory.
>What I like to know: How does this newsgroup think about this machine (chip).

I can only give my opinion; my views do not necessarily represent those of
this group.  No warantee, either expressed or implied, ....

The ARM is a very interesting, and in some ways clever, architecture.  The
ability to do an ALU and SHIFT op in one cycle is surprisingly useful in
some kinds of code, especially the embedded-control, bit-twiddling, graphics-
handling kinds of applications.  The conditional execution (each instruction
hase a 4-bit condition field that must be satisfied for the instruction to
execute) facility is also quite nice, sorta like a skip.  It does have a
three-address architecture.

Its biggest problems are implementation and support.  The address bus is
only 26 bits, faulting handing and memory management are a totally
weird, very fast implementations do not exist, no one is providing
comprehensive support (maybe VLSI tech is doing a better job these days,
but where are the compilers?  UNIX implementations?  etc.), etc.  If I
remember correctly, it also has only 25, or some weird number of, registers,
and only some are available to user code.  One of them is the PC, which
is not good for really high-performance implementations.  The ALU and SHIFT
instructions take 2 cycles.  It has only an address bus and a combined
data/instruction bus.  For best performance, you need more bandwidth.  At
high clock rates, the bus protocols will not work well.

I have seen small graphics kernels on which the ARM does better than any
vanilla RISC in terms of cycle count.  But vanilla RISCs win in total
time (shorter cycle).  Most of the implementation problems could be solved,
but who is solving them?