Path: utzoo!yunexus!geac!geaclib!daveb
From: daveb@geaclib.UUCP (David Collier-Brown)
Newsgroups: comp.arch
Subject: Re: Lisp "future" instruction in 88k hardware.
Message-ID: <3401@geaclib.UUCP>
Date: 10 Nov 88 02:03:04 GMT
Article-I.D.: geaclib.3401
References: <917@taux01.UUCP>
Organization: GEAC Computers, Toronto, CANADA
Lines: 19

From article <917@taux01.UUCP>, by cjosta@taux01.UUCP (Jonathan Sweedler):

| Isn't this the same principle as scoreboarding in a pipelined
| architecture that is used in many processors today?  In such a design,
| an instruction is put in the pipe, but if another instruction tries to
| read the destination register of the first instruction before the
| result is written into the register, then the pipe is stalled.

   Yup, thats almost exactly what the lispians were generalizing
from.  Its finally become available on silicon that doesn't belong
to a $upercomputer, which tends to imply that it could become
even more "generally" usefull.

--dave
-- 
 David Collier-Brown.  | yunexus!lethe!dave
 Interleaf Canada Inc. |
 1550 Enterprise Rd.   | HE's so smart he's dumb.
 Mississauga, Ontario  |       --Joyce C-B