Path: utzoo!utgpu!attcan!uunet!cbmvax!rutgers!apple!baum
From: baum@Apple.COM (Allen J. Baum)
Newsgroups: comp.arch
Subject: Re: HW v. SW (was RISC v. CISC --more misconceptions)
Message-ID: <20353@apple.Apple.COM>
Date: 10 Nov 88 17:42:57 GMT
References: <866@cernvax.UUCP> <5195@cbmvax.UUCP> <646@fabscal.UUCP>
Reply-To: baum@apple.UUCP (Allen Baum)
Organization: Apple Computer, Inc.
Lines: 16

[]
>In article <646@fabscal.UUCP> dorn@fabscal.UUCP (Alan Dorn Hetzel Jr.) writes:
>...For example, the Motorola DSP-56000 has an address modifier mode called
>"carry-reversal" which causes address increments to start on the high bit
>and carry downwards.  This properly produces the order of addresses needed
>for the FFT bit-reversed addressing mode, and does it with NO extra clock
>cycles above the standard increment mode.

While it takes no extra cycles, it probably causes the speed of the adder to 
increase, possibly increasing the overall cycle time. This is a classic
RISC-CISC tradeoff. Given the applications the 56000 was intended for, they
probably made the tradeoff correctly. Its a pretty clever hack.

--
		  baum@apple.com		(408)974-3385
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