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Path: utzoo!attcan!uunet!lll-winken!lll-tis!helios.ee.lbl.gov!pasteur!ames!nrl-cmf!cmcl2!rutgers!att!ihlpl!jhh
From: jhh@ihlpl.ATT.COM (Haller)
Newsgroups: comp.sys.misc,news.groups
Subject: Re: comp.sys.next, etc.
Summary: Omitting parity makes machine more reliable
Message-ID: <7471@ihlpl.ATT.COM>
Date: 2 Nov 88 14:48:27 GMT
References: <5178@medusa.cs.purdue.edu> <40975@yale-celray.yale.UUCP> <575@micropen>
Organization: AT&T Bell Laboratories - Naperville, Illinois
Lines: 17

In article <575@micropen>, dave@micropen (David F. Carlson) writes:
> 
> Is there any good answer for omitting parity checks on memory?
> 

The MTBF for a machine without parity is larger than a machine with
parity.  This is because the additional parts all have non-zero failure
rates, but parity adds nothing to the reliability of the system,
unlike EDC, which allows one to continue using the computer even in
the face of a single memory problem.  Parity circuitry, in the simplist
design, also slows down access to memory.

So what do you gain with parity - a more timely notification that
there is something incorrect in the memory.  This allows an increase
in reliance on the results produced by the computer, but doesn't
increase the reliability by anything.

John Haller att!ihlpl!jhh  or jhh@ihlpl.att.com