Path: utzoo!utgpu!attcan!uunet!yale!wald-david
From: wald-david@CS.YALE.EDU (david wald)
Newsgroups: comp.sys.next
Subject: 68030 cache (was Re: NeXT & "threads")
Message-ID: <42166@yale-celray.yale.UUCP>
Date: 4 Nov 88 00:53:43 GMT
References: <10736@reed.UUCP> <363@thor.wright.EDU> <8810291732.AA27129@ghidrah.eecg.toronto.edu>
Sender: root@yale.UUCP
Reply-To: wald-david@CS.YALE.EDU (david wald)
Organization: Yale University Computer Science Dept, New Haven CT  06520-2158
Lines: 17

In article <8810291732.AA27129@ghidrah.eecg.toronto.edu>
okrieg@eecg.toronto.edu ("Orran Y. Krieger") writes:
>I believe that the current version of MACH on Next does not support
>multiple processors. However even when it will, each NEXT CPU board has
>its own local memory etc... Does anyone know if when multiple processor
>boards can be put in will they have a global physical address space
>(i.e. processor A can address processor B`s memory). Hmmm no cache so
>I guess that there would be no consistency problem...

Unless you're talking about a 680x0, x >= 2.  The in-chip cache could get
just as screwed up in a multi-processor - common-memory situation.


============================================================================
David Wald                                              wald-david@yale.UUCP
						       waldave@yalevm.bitnet
============================================================================