Path: utzoo!utgpu!attcan!uunet!husc6!rutgers!gatech!gt-eedsp!jensen
From: jensen@gt-eedsp.UUCP (P. Allen Jensen)
Newsgroups: comp.sys.next
Subject: Re: NeXT Memory - No Error Checking or
Summary: Reason for no parity/ECC according to NeXT salesperson
Message-ID: <553@gt-eedsp.UUCP>
Date: 3 Nov 88 14:49:23 GMT
References: <549@gt-eedsp.UUCP> <207400001@inmet> <956@accelerator>
Organization: Georgia Institute of Technology
Lines: 15

In article <956@accelerator>, abali@baloo.eng.ohio-state.edu (Bulent Abali) writes:
> If NeXT didn't put ECC in it's memory, I'll say it is a tradeoff
> to get performance, not because of cost. If I were a microprocessor
> designer, I would generate the check bits or parity on the chip, 
> rather than trying to squeeze in a larger cache. 

According to the NeXT salesperson I talked to, the reason was COST not
performance.  I am not an expert on memory hardware, but it doesn't seem
reasonable to me that parity should cause a performance hit.

-- 
P. Allen Jensen
Georgia Tech, School of Electrical Engineering, Atlanta, GA  30332-0250
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