Path: utzoo!attcan!uunet!husc6!mailrus!purdue!decwrl!hplabs!hpl-opus!jewett From: jewett@hpl-opus.HP.COM (Bob Jewett) Newsgroups: comp.sys.next Subject: Re: PaRITY (was NeXT Memory - No Error Checking or Parity !) Message-ID: <69070002@hpl-opus.HP.COM> Date: 5 Nov 88 09:35:20 GMT References: Organization: HP Labs, High Speed Electronics Dept., Palo Alto, CA Lines: 26 > Today's memory is VERY reliable and (he said) it virtualy never fails one > cell at a time; usually the entire bank or group of banks fail. This is not correct. Present commercial 1 meg DRAMs often have one-bit soft errors. In this context, often means about once per year on a system that has 32 meg of RAM. > The logic used for parity checking can introduce more errors into the > system if it should fail. Due to the types of circuits involved, the parity checking system is much less likely to introduce errors than the memory itself. > Implementing parity on a system slowes the system down. With 100ns memories > and 200ns to compute parity, one cannot run a system as fast as without > parity. This is also not correct. Parity checking can be pipelined, so that the parity checker stops the system within 200 ns if an error occurs, but no delay is introduced for error-free accesses. At any rate, parity checking on either nine or 33 bits, using 74AS280 TTL circuits takes less than 20 nanoseconds. Bob Jewett (see previous response for disclaimer)