Path: utzoo!attcan!uunet!csdev!ll1a!spl1!laidbak!att!rutgers!mailrus!bbn!inmet!ishmael!inmet!callen
From: callen@inmet
Newsgroups: comp.sys.next
Subject: Re: NeXT Memory - No Error Checking or
Message-ID: <8534@spl1.UUCP>
Date: 31 Oct 88 15:04:00 GMT
References: <549@gt-eedsp.UUCP>
Sender: news@spl1.UUCP
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Nf-ID: #R:gt-eedsp.UUCP:-54900:inmet:207400001:000:1009
Nf-From: inmet!callen    Oct 31 10:04:00 1988


>/* Written 12:32 am  Oct 30, 1988 by james@bigtex.UUCP in inmet:comp.sys.next 
>For those not aware: the Intel 80x88 family has a design flaw that
>requires external hardware to disable NMI.  Without such hardware it
>is not possible to prevent the system from randomly crashing when NMIs
>are used.

NMI means "Non Maskable Interrupt" and it's considered a feature, not a bug.

Getting back to parity, I'm surprised, too, that NeXT didn't use either
parity or ECC. There are a number of single-chip ECC solutions available,
so I can't believe that the cost would have gone up THAT much. But then,
I'm not a memory designer, either. 

I am under the (possible wrong) impression that soft memory errors are
often caused by cosmic rays streaking through one of the cells in a DRAM 
and discharging it, and that higher density memories are MORE susceptible
to this type of error. Is there a memory expert listening who can comment?

-- Jerry Callen
   callen@inmet.inmet.com
   ...{uunet,harvard}!inmet!callen