Path: utzoo!attcan!uunet!csdev!ll1a!spl1!laidbak!att!pacbell!ames!mailrus!bbn!jr@bbn.com From: jr@bbn.com (John Robinson) Newsgroups: comp.sys.next Subject: Re: PaRITY (was NeXT Memory - No Error Checking or Parity !) Keywords: Memory,errors,parity Message-ID: <8588@spl1.UUCP> Date: 3 Nov 88 06:58:14 GMT References: <549@gt-eedsp.UUCP> <7493@well.UUCP> Sender: news@spl1.UUCP Reply-To: jr@bbn.com (John Robinson) Organization: BBN Systems and Technologies Corporation, Cambridge MA Lines: 18 In-reply-to: patterso@hardees.rutgers.edu (Ross Patterson) In article , patterso@hardees (Ross Patterson) writes: > I understand that IBM's 3090 series has Double-bit >Correct/Triple-bit Detect logic. Neato. No, I think hype. IBM's game is confidence in their product, and I am sure this sells in their customer base a lot. A DRAM failure takes out one bit per word, and if you pay attention at all to the correction logs you should get the memory chip or board fixed long before two DRAMs in the same bank fail, or do 3090's build their gigabyte out of 16k's :-) ? On the other hand 4kby256 chips might plausibly want 4-bit-correction, for which the cost would make even IBM's customer cringe. I agree that parity/edac ought to be available, and it'll probably come along eventually by third party or whatever. -- /jr jr@bbn.com or bbn!jr