Path: utzoo!attcan!uunet!ncrlnk!ncrcae!ece-csc!mcnc!xanth!nic.MR.NET!tank!uxc!uxc.cso.uiuc.edu!urbsdc!aglew
From: aglew@urbsdc.Urbana.Gould.COM
Newsgroups: comp.arch
Subject: Re: HW v. SW (was RISC v. CISC --mo
Message-ID: <28200235@urbsdc>
Date: 11 Nov 88 01:49:00 GMT
References: <646@fabscal.UUCP>
Lines: 9
Nf-ID: #R:fabscal.UUCP:646:urbsdc:28200235:000:492
Nf-From: urbsdc.Urbana.Gould.COM!aglew    Nov 10 19:49:00 1988


>Well, when you get right down to it, bit-reversal is the sort of operation
>which when done *properly* in hardware, should take *zero* cycles, being
>the sort of thing you reduce to an addressing mode.

An addressing mode!!!!!  An array of wires, maybe, but man, addressing memory
is slow and getting slower. RISCs can get away with it by caching and 
prefetching, but caching and prefetching does not do you very much good
for large lookup tables when the inputs are uniformly distributed.