Path: utzoo!attcan!uunet!hsi!mfci!frisch
From: frisch@mfci.UUCP (Michael Frisch)
Newsgroups: comp.arch
Subject: VLIW
Summary: We already pipeline
Message-ID: <554@m3.mfci.UUCP>
Date: 12 Nov 88 13:43:56 GMT
References: <70@armada.UUCP> <28200228@urbsdc> <5087@mit-vax.LCS.MIT.EDU>
Sender: frisch@mfci.UUCP
Reply-To: frisch@mfci.UUCP (Michael Frisch)
Organization: Multiflow Computer Inc., Branford Ct. 06405
Lines: 38

In article <5087@mit-vax.LCS.MIT.EDU> spectre@mit-vax.UUCP (Joseph D. Morrison) writes:
>
>So I think we were actually arguing about "which is better for getting
>parallelism; pipelining or VLIW?" Phrased that way, I think the answer
>is obviously "use both".
>
>If each of your functional units takes 4 cycles to perform its
>operation, and you have a VLIW machine with 8 functional units, your
>average throughput will be 2 instructions per cycle. The obvious thing
>to do is to use pipelined functional units, and get the 8 instructions
>per cycle you deserve :-)
>
>Naturally, as soon as you do this you will need some mechanism for
>handling the various conflicts that occur when two instructions in the
>pipeline want to use the same register. This is when you can use
>scoreboarding, or whatever you want.
>
>In fact, what better way to test pipeline strategies! With all those
>functional units, the pipeline management will be pretty hairy...
>
This is already done in Multiflow's VLIW ... instructions which take
more than one cycle (floating add, floating multiply, memory references)
are pipelined, with the pipes exposed to the compiler.  So these operations
can each be initiated every cycle.  The pipelining is managed in software,
at compile time, rather than by a scoreboard at runtime.  It may be hairy,
but a) the compiler has much more information available to it than the limited
look-ahead of a scoreboard, b) the compiler can rearrange operations as
needed to keeps the pipes full while the scoreboard can at best execute those
future operations which happen to be data-ready, and c) making the hardware
simpler (i.e., no scoreboard) makes the system more cost-effective.

(Someone asked about integer multiplies .. they're done in one cycle in
hardware already ... its the flops and memory refs which gain from pipelining).

                                       Mike Frisch

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The opinions above are mine and not necessarily those of my employer.