Path: utzoo!attcan!uunet!munnari!mimir!hugin!augean!idall
From: idall@augean.OZ (Ian Dall)
Newsgroups: comp.arch
Subject: Re: HW v. SW (was RISC v. CISC --mo
Message-ID: <420@augean.OZ>
Date: 14 Nov 88 06:45:05 GMT
References: <646@fabscal.UUCP> <28200235@urbsdc>
Reply-To: idall@augean.OZ (Ian Dall)
Organization: Engineering Faculty, University of Adelaide, Australia
Lines: 29

In article <28200235@urbsdc> aglew@urbsdc.Urbana.Gould.COM writes:
>
>>Well, when you get right down to it, bit-reversal is the sort of operation
>>which when done *properly* in hardware, should take *zero* cycles, being
>>the sort of thing you reduce to an addressing mode.
>
>An addressing mode!!!!!  An array of wires, maybe, but man, addressing memory
>is slow and getting slower. RISCs can get away with it by caching and 
>prefetching, but caching and prefetching does not do you very much good
>for large lookup tables when the inputs are uniformly distributed.

If the main use for the bitreverse instruction is going to be for FFTs then
an addressing mode might be appropriate. If it is more generally useful then
perhaps a general instruction is the way to go. I can't think of any
application besides FFTs which would be significantly affected by the speed
of the bit reverse operation so an addressing mode might not be so silly.

FFT sequencing involves a fairly tight loop containing an operation like:

increment (offset)
load (base_address + bitreversal(offset))

On most conventional machines it is actually more efficient to do it
differently.

-- 
 Ian Dall           life (n). A sexually transmitted disease which afflicts
                              some people more severely than others.
idall@augean.oz