Path: utzoo!attcan!uunet!seismo!sundc!pitstop!sun!amdcad!ames!sgi!karsh@trifolium.SGI.COM From: karsh@trifolium.SGI.COM (Bruce Karsh) Newsgroups: comp.arch Subject: ZISC computers Keywords: ZISC Message-ID: <22115@sgi.SGI.COM> Date: 16 Nov 88 08:39:49 GMT Sender: daemon@sgi.SGI.COM Reply-To: karsh@trifolium.UUCP (Bruce Karsh) Organization: Silicon Graphics, Inc., Mountain View, CA Lines: 66 Why bother with reduced instruction set computers when a computer really doesn't need any instructions per se at all? At the end of the RISC road is the ZISC, Zero Instruction Set Computer. One way to look at the RISC processor design paradigm is that you should not include any feature into the design which has not been proven to be worth its implementation cost. I.e., remove extraneous features. If you are looking for something extraneous to remove from a computer's instruction set, it might be advantageous to consider removing the opcode field. The opcode takes up space in each instruction and takes time to be decoded. So let's get rid of them! But if you don't have an opcode in each instruction, how can the CPU decide which operation to apply to the operands? The selection of the operation can be determined implicitly from the address of the operands. For example, address zero can be the input to an accumulator, address 4 can be the accumulator's sum, address 8 can be the input to a multiplier, address 12 can be the multiplier's output, etc. You can even map the program counter to some memory address. By moving data into these special addresses, computation is caused to happen. These special addresses otherwise look to programs as if they were normal memory addresses. Using special addresses to control devices is not a new idea. Peripheral devices have been controlled this way for a long time. But it's interesting that you can use this control method for controlling devices within the computer as well as outside. In fact this can be the only control method that the computer has. The program for such a system would consist of a list of ordered pairs of addresses. It would execute by moving data from (for example) the first address in the pair to the second address in the pair (or vice versa). Flow of control is changed by moving data into the address mapped into the program counter. There is nothing for the instruction sequencer to do except to perform alternating fetches and stores. Therefore the instruction sequencer can be fast ... even faster than the computational units. You can acheive lots of parallelism by replicating the computational units at multiple addresses. (For instance, multiplier inputs can be located at addresses 8, 256+8, 512+8, 768+8 and multiplier outputs can be located at addresses 12, 256+12, 512+12 and 768+12). Compilers will generate code which sequences the accesses to special addresses so that they are not accessed before their computations are complete. One neat feature of this architecture is that if you consider the address ordered pairs as position vectors in cartesian space, then the program traces out a path through the space. Loops within the program appear as polygons in the space. Another neat feature is that DMA devices can get at computational units within the computer. For example, an A/D converter can be DMA'd directly into a multiply-accumulator; a list of vertices can be DMA'd directly into a matrix times vector multiplier... etc. I'v never seen a computer architecture such as this (ZISC) proposed before. I'd like to know if anybody else has suggested this idea before. -- Bruce Karsh karsh@sgi.com "Nature uses only the longest threads to weave her patterns, so each small piece of her fabric reveals the organization of the entire tapestry".