Path: utzoo!attcan!uunet!pyrdc!pyrnj!rutgers!mcnc!rti!trt
From: trt@rti.UUCP (Thomas Truscott)
Newsgroups: comp.arch
Subject: Re: A simple question on RISC
Summary: more examples of slow CISC instructions
Message-ID: <2577@rti.UUCP>
Date: 16 Nov 88 19:19:05 GMT
References: <6544@xanth.cs.odu.edu> <75577@sun.uucp> <1618@imagine.PAWL.RPI.EDU> <32376@bbn.COM>
Organization: Research Triangle Institute, RTP, NC
Lines: 69

> >Can anyone tell me *why* some of these microcoded instructions were
> >slower than a combination of simpler instructions on the same machine?

Henry Spencer answered this well -- the performance-critical instructions
(such as load/store/move) get enormous attention by the hardware people
and by the micro-coders.  Other instructions often lack necessary hardware,
or may be poorly-microcoded.  Examples abound, many concern the VAX
because it is the flagship of CISC and is so popular and accessible.

Here are some examples on other machines.  These examples should
not be construed as criticism of these machines,
they are simply the machines with which I am familiar.

PDP 11/70 (and probably most other models)
	The MOV instruction is the workhorse of this machine,
	and the designers no doubt worked hard to make it fast.
	They did a good enough job that
		JMP	LABEL
	is slower than
		MOV	#LABEL,pc	/ move address into program counter
	MOV is faster than JMP in all cases, including some such as
		MOV	@(r2)+,pc
	that JMP cannot even support.
	So JMP is a useless instruction on the PDP.

	The RTS (return from subroutine) call is heavily used
	on the PDP.  Yet
		RTS	r5
	is slower than the equivalent
		MOV	(r5)+,pc
	So RTS is a useless instruction on the PDP.

	There are other pointless instructions on the PDP (remember MARK?)
	and this on a machine with not that many instructions!
	Different models of PDP had different instruction sets,
	peculiarities with some of the instructions,
	and peculiarities with some of the addressing modes.
	So compiler writers wrote for the common subset,
	leaving the peculiar things unused, so they were "useless".
	
	What is wrong with having useless instructions?
	I am sure various RISC papers address this topic.

Gould PowerNode 9050
	There is a nice "Add-Bit-To-Register" instruction that
	can add any power of 2 to a register,
	which the timing table claims* takes one cycle.
	(* Vendor timing tables always have total disclaimers.)
	But it actually takes several cycles.
	The compiler writers are well aware of this,
	and never use this instruction.
	I estimate that, for one reason or another,
	over half of the PowerNode instructions are never* used
	(* of course the diagnostics check their operation).

Gould PowerNode 6000
	This is a somewhat slower Gould model, which micro-codes
	the multiple-bit-shift operation as a several single bit shifts.
	The compiler writers are well aware of this,
	and use various tricks to minimize (or eliminate) the shift distance.

There are plenty more machines out there, but this is getting a bit long.

> So, aside from implementation details, I see no "RISC superiority"
> arguments here.

One of the arguments against CISC is that they have
far too many "implementation details".
	Tom Truscott