Path: utzoo!attcan!uunet!pyrdc!pyrnj!rutgers!apple!baum From: baum@Apple.COM (Allen J. Baum) Newsgroups: comp.arch Subject: Re: Why is the RT slow? Message-ID: <20791@apple.Apple.COM> Date: 17 Nov 88 18:44:54 GMT References: <5046@polya.Stanford.EDU> <691@quintus.UUCP> Reply-To: baum@apple.UUCP (Allen Baum) Organization: Apple Computer, Inc. Lines: 20 [] I don't think its very mysterious why the RT performance is so bad. Aside from the dark rumours that the architecture was deliberately crippled so as not to impact existing product lines, it (the implementation, NOT the architecture) was not whizzy because of engineering tradeoffs. They stuck to a microcomputer bus, they used a process technology that was barely state-of-the-art (or wasn't by the time they finished, anyway), did not have a cache. It only ran at 6MHz! Why bother with a cache! They made lots of tradeoffs for backwards compatibility with existing systems. However, don't believe that a flawed implementation means the architecture is flawed. It may be flawed, but I've seen no convincing arguments of in this newsgroup. A 33Mhz version of the chip, with cache, should scream. Just like a 33Mhz version of an R3xxx, or a 29000, or an 88xxx ..... I see very little in the architecture that would make, say, a 10% difference in performance, which is equivalent to a four month lead time. -- baum@apple.com (408)974-3385 {decwrl,hplabs}!amdahl!apple!baum