Path: utzoo!attcan!uunet!husc6!mailrus!uflorida!haven!uvaarpa!babbage!mac3n
From: mac3n@babbage.acc.virginia.edu (Alex Colvin)
Newsgroups: comp.arch
Subject: Re: ZISC computers
Summary: New England Digital
Keywords: ZISC
Message-ID: <411@babbage.acc.virginia.edu>
Date: 17 Nov 88 21:58:41 GMT
References: <22115@sgi.SGI.COM>
Organization: University of Virginia
Lines: 28

In article <22115@sgi.SGI.COM>, karsh@trifolium.SGI.COM (Bruce Karsh) writes:
> Why bother with reduced instruction set computers when a computer
> really doesn't need any instructions per se at all?  At the end of the
> RISC road is the ZISC, Zero Instruction Set Computer.
> 
> I'v never seen a computer architecture such as this (ZISC) proposed
> before.  I'd like to know if anybody else has suggested this idea
> before.

This is the Able compter by New England Digital.  These are used in the
Synclavier digital music synthesizers.  At Dartmouth we also used them for
network routers.

I don't have a manual with me, but the basic idea is as you suggest.  There
is no opcode field.  All instructions are MOVE.  There are about 16
registers, two of which are PCs (one for interrupts).  Memory is addressed
indirectly through registers.  A couple of special sources/destinations get
at the ALU.  There are I/O addresses as well.

An interesting feature is the completely asynchronous instruction cycle.
You can do a MOVE from the keyboard to the printer, which will hang the
processor waiting for you to type.  Needless to say, there are interrupts
and status registers so you can avoid this.

The processor used to be 16 bit words, TTL components.  By now it's
probably bigger and faster, with special interfaces to memory.  There's
also something else called Able, so the name may have changed.  Anyone at
Dartmouth or True know?