Path: utzoo!attcan!uunet!munnari!basser!andrewt
From: andrewt@basser.oz (Andrew Taylor)
Newsgroups: comp.arch
Subject: Re: Why is the RT slow?
Message-ID: <1620@basser.oz>
Date: 18 Nov 88 05:02:38 GMT
References: <5046@polya.Stanford.EDU> <cXU-XCy00V48ECDWt=@andrew.cmu.edu> <691@quintus.UUCP>
Reply-To: andrewt@basser.oz (Andrew Taylor)
Organization: Dept of Comp Sci, Uni of Sydney, Australia
Lines: 26

>From: jk3k+@andrew.cmu.edu (Joe Keane)
> I get the impression that they were paranoid about code space, giving a
> too-complicated instruction set.  To wit:
> [...]
> *  The `short' instructions.  No rhyme or reason other than that they save 2
> bytes and do common things.

Unlike the 801 the RT has no instruction cache (an economic decision).
The designers introduced 2 byte instructions in an attempt
to compensate for the lack of cache. Unfortunately this required reducing
the number of registers from 32 to 16. I vaguely recall hearing that the
no cache decision was later regretted.

The first RT processor because of a problem with memory management exceptions
did not allow the execution of the load/store instructions to be
overlapped with subsequent instructions. As load/store instructions
take 5-6 cycles this was a significant handicap.

The 2nd RT processor (sometimes called the RT/APC) allowed load/store
instructions to be overlapped. This plus the clock-speed being almost
doubled made it much faster. The only benchmark I've seen puts it
between a SUN 3/50 and a SUN 3/60.

More RT models came out this year. I know nothing about them.

Andrew