Path: utzoo!utgpu!watmath!clyde!bellcore!texbell!killer!ames!mailrus!uflorida!gatech!psuvax1!schwartz@shire.cs.psu.edu From: schwartz@shire.cs.psu.edu (Scott Schwartz) Newsgroups: comp.arch Subject: Re: Why is the RT slow? Summary: spiffy ram chips Keywords: risc RT IBM Message-ID: <4129@psuvax1.cs.psu.edu> Date: 19 Nov 88 00:44:03 GMT References: <5046@polya.Stanford.EDU> <2921@ima.ima.isc.com> Sender: news@psuvax1.cs.psu.edu Reply-To: schwartz@shire.cs.psu.edu (Scott Schwartz) Organization: Pennsylvania State University, Computer Science Lines: 9 In-reply-to: johnl@ima.ima.isc.com (John R. Levine) In article <2921@ima.ima.isc.com>, johnl@ima (John R. Levine) writes: > Also they decided to design the CPU to work without a >cache, basically because they guessed wrong about where memory technology was >going. I'm told that the new ones (615x) use 3090 technology memory. I really hope it's helping :-) -- Scott Schwartz