Path: utzoo!utgpu!watmath!clyde!att!alberta!calgary!dataspan!deraadt From: deraadt@dataspan.UUCP (Theo De Raadt) Newsgroups: comp.arch Subject: Re: A simple question on RISC Message-ID: <254@dataspan.UUCP> Date: 20 Nov 88 20:10:06 GMT References: <6544@xanth.cs.odu.edu> <28200238@urbsdc> Organization: DataSpan Inc., Calgary AB Canada Lines: 23 >Can anyone tell me *why* some of these microcoded instructions were >slower than a combination of simpler instructions on the same machine? >I am not debating CISC vs RISK here since both cases run on the *same* >(cisc) machine. If nothing else the second case must have resulted in >more memory accesses for instruction fetches. Was the difference >simply incompetence on the part of the micro code writer, or is there >some reason for this. > > Ian Dall I don't know, just that on the CISC processor I am most familiar with, the bus cycles are longer, so that all sorts of slow/fast/synchronous/ asynchronous types of memory and IO can be talked to easily without having to add much external hardware, the circuitry to talk to any type of memory is built into the chip. Of course, I guess that they should have been shorter, but then I don't know if that has much to do with the instruction set timing at all.