Path: utzoo!attcan!uunet!portal!cup.portal.com!bcase
From: bcase@cup.portal.com (Brian bcase Case)
Newsgroups: comp.arch
Subject: Re: A simple question on RISC
Message-ID: <11562@cup.portal.com>
Date: 20 Nov 88 21:36:17 GMT
References: <6544@xanth.cs.odu.edu> <75577@sun.uucp> <1618@imagine.PAWL.RPI.EDU> <419@augean.OZ> <392@ksr.UUCP>,	<7723@aw.sei.cmu.edu> <oXV-=Wy00V4109jmdK@andrew.cmu.edu>
Organization: The Portal System (TM)
Lines: 17

>Good idea; let's try it:
>
>        mov     lower,i
>        bra     entry
>body    foo
>        add     step,i
>entry   cmp     i,upper
>        bge     body
>
>Statically, same number of instructions; dynamically, less except in the
>zero-trip case.  But look, the add, compare, and branch are consecutive.

Ok, but notice the label in the middle of the add-compare-branch sequence?
I don't think it is possible to specify the ACB instruction in a version
that has a branch destination in the middle!  This is one of the points of
RISC:  Hey, *I'M* the compiler, let *me* decide on the semantics of
instruction sequences.