Path: utzoo!utgpu!watmath!clyde!att!osu-cis!tut.cis.ohio-state.edu!mailrus!uflorida!beach.cis.ufl.edu!seeger
From: seeger@beach.cis.ufl.edu (F. L. Charles Seeger III)
Newsgroups: comp.arch
Subject: Re: Gates vs Transistors (was: Some facts about the Acorn RISC Machine)
Keywords: Acorn RISC ARM
Message-ID: <19323@uflorida.cis.ufl.EDU>
Date: 22 Nov 88 01:53:32 GMT
References: <543@acorn.UUCP> <18267@ames.arc.nasa.gov>
Sender: news@uflorida.cis.ufl.EDU
Reply-To: seeger@beach.cis.ufl.edu (F. L. Charles Seeger III)
Organization: UF EE Dept
Lines: 39

Well, I haven't seen a posted answer to this:

In article <18267@ames.arc.nasa.gov> lamaster@ames.arc.nasa.gov.UUCP (Hugh LaMaster) writes:
|In article <543@acorn.UUCP> RWilson@acorn.co.uk writes:
|>respectively. The ARM comprises 24,000 transistors (circa 8,000 gates).
|
|I know this must be obvious to many hardware types out there, but, is this
|ratio of transistors/gates typical for CMOS?

I can't speak much about real world practice, but can give a brief
background, since no one else has answered publicly.  Of course, counting
these things is a bit open to interpretation, e.g. what is a typical
gate? how to count a PLA or memory cell? etc.  I prefer to count
transistors and IO pads, realizing, of course, that yield and die area
are the most important economic measures, for a given process.

A fully static CMOS gate will typically have two transistors
per input signal.  This is why CMOS transistors are sometimes counted
in pairs (one n-type and one p-type).  If we assume as our reference
gates with two inputs, then we should expect 4 transistors/gate.
However, CMOS is very rich in the variety of logic circuit techniques
that can be used, most of which reduce the transistor count but may
decrease speed, increase circuit complexity and create debugging
problems (i.e. it tends to be easier to debug fully static designs).
Good simulation tools make these trade-offs more predictable.  For
example, these logic structures include pseudo-nmos, dynamic, clocked,
domino, pass transistors and cascade voltage switches.  The use of
dynamic logic is signified by a *minimum* clock rate for a part, which
is common for microprocessors.  Weste and Eshraghian's book,
_Principles_of_CMOS_VLSI_Design_A_Systems_Perspective_ ('85), is a good
introduction to these logic families.

I hope this wasn't too far off from the answer that you were seeking.
Chuck

--
  Charles Seeger            216 Larsen Hall
  Electrical Engineering    University of Florida
  seeger@iec.ufl.edu        Gainesville, FL 32611