Path: utzoo!attcan!uunet!ubvax!ames!lamaster
From: lamaster@ames.arc.nasa.gov (Hugh LaMaster)
Newsgroups: comp.arch
Subject: Re: Gates vs Transistors (was: Some facts about the Acorn RISC Machine)
Keywords: Acorn RISC ARM
Message-ID: <18574@ames.arc.nasa.gov>
Date: 23 Nov 88 03:26:24 GMT
References: <543@acorn.UUCP> <18267@ames.arc.nasa.gov> <19323@uflorida.cis.ufl.EDU>
Reply-To: lamaster@ames.arc.nasa.gov.UUCP (Hugh LaMaster)
Organization: NASA Ames Research Center, Moffett Field, Calif.
Lines: 29

In article <19323@uflorida.cis.ufl.EDU> seeger@beach.cis.ufl.edu (F. L. Charles Seeger III) writes:

>I can't speak much about real world practice, but can give a brief
>background, since no one else has answered publicly.  Of course, counting
>these things is a bit open to interpretation, e.g. what is a typical
>gate? how to count a PLA or memory cell? etc.  I prefer to count

Well, what I am really driving at is "4 input nand gate equivalents".
(Or 2 input nand gate equivalents, if that makes more sense...)
The reason is just that there is no convenient way to judge CPU
complexity by "number of transistors" without knowing a lot about the
technology.  I am looking for a ROUGH estimate of complexity independent
of the number of transistors.

I may be wrong, but may guess is that there is some easy and CONSISTENT
way to measure CPU complexity which is ROUGHLY correct (within a factor
of two).  Am I the only person out there wondering how much logic can be
packed onto one of those new GaAs micros, and would like to compare that
to a uVAX or MIPS chip?  Since this isn't going to be of use to
marketeers, a simple measure which is USUALLY only slightly misleading
would be of use.



-- 
  Hugh LaMaster, m/s 233-9,  UUCP ames!lamaster
  NASA Ames Research Center  ARPA lamaster@ames.arc.nasa.gov
  Moffett Field, CA 94035     
  Phone:  (415)694-6117